EDA技术与VHDL期末复习程序汇总

参考教材 EDA技术与VHDL(第3版)潘松 黄继业编著

1. 教材课后答案

3-2 If-then语句4选1选择器（P92）

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41 IS

PORT ( a,b,c,d: IN std_logic;

s: IN std_logic_vector(1 downto 0); y : OUT std_logic ); END ENTITY mux41;

ARCHITECTURE one OF mux41 IS BEGIN

PROCESS (a,b,c,d,s) BEGIN

IF s = "00" THEN y <= a ; elsif s="01" THEN y <= b ; elsif s="10" THEN y <= c ; elsif s="11" THEN y <= d ; END IF; END PROCESS;

END ARCHITECTURE one ; 3-2 case语句4选1选择器（P92）

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS PORT(

s: IN STD_LOGIC_VECTOR(1 DOWNTO 0); a, b, c, d: IN STD_LOGIC; y: OUT STD_LOGIC); END mux4;

ARCHITECTURE archmux OF mux4 IS BEGIN

PROCESS(s,a,b,c,d) BEGIN

Case s is

WHEN "00" => y<=a; WHEN "01" => y<=b; WHEN "10" => y<=c; WHEN OTHERS => y<=d; end case; end process; end archmux;

3-3 双2选1选择器（P92）

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUXK IS

PORT ( a1, a2, a3, s0, s1 : IN std_logic; outy : OUT std_logic ); END ENTITY MUXK;

ARCHITECTURE one OF MUXK IS signal tmp: std_logic; BEGIN

PROCESS (a2, a3, s0)

BEGIN

IF s0 = '0' THEN tmp <= a2 ; ELSE tmp <= a3 ; END IF; END PROCESS;

PROCESS (a1, tmp, s1)

BEGIN

IF s1 = '0' THEN outy <= a1 ; ELSE outy <= tmp ; END IF; END PROCESS;

END ARCHITECTURE one ; 3-4-1 1位半减器（P92）

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_suber IS

PORT (x, y : IN STD_LOGIC;

s_out, diff : OUT STD_LOGIC); END ENTITY h_suber;

ARCHITECTURE fh1 OF h_suber is

SIGNAL abc : STD_LOGIC_VECTOR(1 DOWNTO 0) ; BEGIN

abc <= x & y ; PROCESS(abc) BEGIN

CASE abc IS

WHEN "00" => diff <='0'; s_out <='0' ; WHEN "01" => diff <='1'; s_out <='1' ; WHEN "10" => diff <='1'; s_out <='0' ; WHEN "11" => diff <='0'; s_out <='0' ; WHEN OTHERS => NULL ; END CASE; END PROCESS;

END ARCHITECTURE fh1 ;